The present invention relates to a signal processing delay circuit using a high-precision delay line and, in particular, to a signal processing delay circuit which copes with high-density data recording and high-speed data transfer according to improvement of reproduction margin in a signal processing section of a magnetic disk device.
Referring now to FIG. 10, description will be given of a conventional signal processing delay circuit according to an application example thereof to a data acquisition circuit in a magnetic disk device which acquires reproduction data in a data reproducing operation.
FIG. 10 shows the configuration of a data acquisition circuit of the conventional technology in which a window adjustment circuit 101 includes a fixed-delay N-tap delay 102 having N taps, a selector 103 for selecting either one of the outputs from N taps of the delay 102, and a register 104 for accumulating therein selection information of the selector 103.
Next, operation of the window adjustment circuit 101 will be described. Read data 107 read from a disk for reproduction thereof is fed to the N-tap delay 102. An output from a central tap of the delay 102 is inputted to a read phase-locked loop (PLL) 105. From the PLL 105, a clock signal is produced at a timing synchronized with the read data 107. Moreover, in response to the read data 107 fed to the N-tap delay 102, the selector 103 is controlled according to beforehand specified selection information of the register 104 so as to select an optimal tap from the N taps of the delay 102, thereby outputting data from the selected tap. The clock signal outputted from the read PLL 105 and the data outputted from the selector 103 are both supplied to a data latch 106. In the latch 106, the data from the selector 103 is latched by a clock signal from the read PLL 105 to be thereafter outputted as synchronous read data 108.
The N-tap delay 102 as a signal processing delay circuit in the conventional window adjustment circuit 101 includes a plurality of stages of logic gate delay elements.
Moreover, a write compensation circuit in which data positions are compensated for according to a data pattern in the data recording operation includes also a similar signal processing delay circuit.
The prior art is attended with the following problem. Namely, since the signal processing delay circuit includes a plurality of stages of logical gates each having a fixed delay amount, the N-tap delay 102 constituting a window adjusting circuit of the data acquisition circuit has an amount of delay varying with respect to, for example, deviation in quality of the circuit chip, fluctuation in power, and change in temperature. This consequently leads to deviation of the center of the adjusted window.
Furthermore, for the signal processing delay circuit of the type used in the disk device or the like, the minimum delay interval between the taps is limited to the amount of delay associated with one logical gate constituting the circuit. In consequence, it is impossible to achieve a fine delay adjustment with a higher precision for the amount of delay less than that equivalent to one logical gate. For example, the N-tap delay 102 constituting the window adjustment circuit of the data acquisition circuit cannot appropriately set the center of window with a high accuracy. Consequently, data including a large amount of jitter components due to the peak shift or the like cannot be acquired with a high precision, which leads to difficulty in increasing the data recording density. In a high-speed data transfer, the window width becomes smaller and the window loss due to deviation of the center of window becomes relatively increased, which leads to difficulty in increasing the data transfer speed.
Moreover, since the write compensation circuit of the data write circuit also includes a similar signal processing delay circuit, relative positions between the bits of data to be written on a disk cannot be compensated for with a high precision.